› Module 6: Memory Management › 6.2 Paging
M O D U L E

Module 6: Memory Management

Contiguous allocation, fragmentation, paging, and segmentation

6.1 Contiguous Memory Allocation

In contiguous memory allocation, each process is placed into a single, unbroken block of physical memory. The operating system must decide how to partition RAM among multiple resident programs while mitigating memory fragmentation.

Figure 6.1: Internal Fragmentation (Fixed) vs. External Fragmentation (Variable) Fixed Partitioning → Internal Frag OS Kernel P1 (Uses 2.8 MB) Internal Frag (1.2M) P2 (Uses 3.2 MB) 0.8M Variable Partitioning → External Frag OS Kernel Process P1 (Allocated) Free Hole (1.5 MB) Process P3 (Allocated) Free Hole (1.5 MB) External Fragmentation: Total free memory (3 MB) suffices for P4 (2.5 MB), but no single chunk is contiguous!

Figure 6.1: Internal fragmentation wastes space inside allocated slots; external fragmentation breaks free memory into unusable scattered holes.

Dynamic Partition Allocation Strategies

  • First-Fit: Allocate the very first available free block that is large enough. Fast because search terminates on the first match.
  • Best-Fit: Search the entire list to allocate the smallest hole that is large enough. Leaves behind tiny unusable leftover slivers of free space.
  • Worst-Fit: Search the entire list to allocate the largest available hole. Produces the largest leftover hole, which may be useful for subsequent allocations.

6.2 Paging

Paging is a non-contiguous memory management scheme that completely eliminates external fragmentation. Physical memory is divided into fixed-size blocks called frames, while logical (virtual) memory is divided into blocks of the exact same size called pages.

Figure 6.2: Logical to Physical Address Translation via Page Table & TLB Logical Address (CPU) Page # p Offset d Page # Frame # 0 6 1 2 2 9 3 1 Physical Memory Address Frame # f Offset d Offset passes through completely unchanged Hardware Speedup: Translation Look-aside Buffer (TLB) caches recent Page → Frame lookups.

Figure 6.2: Every CPU logical address split into page number (p) and offset (d). The page table maps p to physical frame f, while d passes through unchanged.

Translation Look-Aside Buffer (TLB)

Because the page table itself lives in main memory, every memory reference requires two accesses: one for the page table entry, and one for the actual byte. To accelerate translation, modern CPUs include a Translation Look-aside Buffer (TLB) — an ultra-fast hardware associative cache storing recent $langle ext{page}, ext{frame} angle$ mappings.

Effective Memory Access Time (EMAT) Formula:

EMAT = Hit_Ratio × (TLB_access + Memory_access) + (1 − Hit_Ratio) × (TLB_access + 2 × Memory_access)

6.3 Segmentation

While paging divides memory into uniform physical blocks transparent to the programmer, Segmentation reflects the programmer's logical view of memory. A program is viewed as a collection of variable-length logical units called segments (e.g. main program, procedures, stack, global variables, symbol tables).

Figure 6.3: Segmentation — Logical Segments Mapped via Segment Table Logical User View Seg 0: Main Function Seg 1: Call Stack Seg 2: Symbol Table Seg 3: Sqrt Subroutine Segment Table Seg Limit Base 0 1000 1400 1 400 6300 2 400 4300 3 1100 3200 Physical Memory Seg 0 (Base: 1400) Seg 3 (Base: 3200) Seg 2 (Base: 4300) Hardware checks: if offset d > Limit, CPU raises Trap (Addressing Error / Segfault).

Figure 6.3: Each segment maps to physical memory via a Base (start address) and Limit (length). Offset must be strictly less than Limit.

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Yukti Mascot