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Module 6 Final Quiz: Main Memory Management MCQs
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1
What hardware component is responsible for translating logical (virtual) memory addresses to physical RAM addresses at runtime?
A.
Direct Memory Access (DMA) controller
B.
Memory Management Unit (MMU)
C.
Arithmetic Logic Unit (ALU)
D.
Interrupt Controller (APIC)
Explanation & Key
Correct Answer:
2
What is the difference between Internal and External Fragmentation?
A.
Internal fragmentation occurs on disk; external fragmentation occurs in RAM
B.
Internal fragmentation is unused memory wasted INSIDE an allocated fixed block; external fragmentation is free memory scattered OUTSIDE allocated blocks in small non-contiguous slices
C.
Internal fragmentation is eliminated by paging; external fragmentation is caused by paging
D.
Internal fragmentation affects the CPU cache; external affects the heap
Explanation & Key
Correct Answer:
3
Given a 32-bit logical address space and a 4 KB page size, how many bits are used for the page offset (d) and page number (p)?
A.
Offset: 10 bits ($2^{10}=1024$), Page Number: 22 bits
B.
Offset: 12 bits ($2^{12}=4096$), Page Number: 20 bits ($32 - 12$)
C.
Offset: 16 bits, Page Number: 16 bits
D.
Offset: 8 bits, Page Number: 24 bits
Explanation & Key
Correct Answer:
4
What is the function of the Translation Lookaside Buffer (TLB)?
A.
To store dirty data pages on disk
B.
A high-speed, small associative hardware cache in the MMU that stores recent virtual-to-physical page mappings to avoid extra memory lookups
C.
To compile machine instructions into microcode
D.
To compress virtual memory pages
Explanation & Key
Correct Answer:
5
Calculate Effective Memory Access Time (EMAT) if RAM access time is 100 ns, TLB lookup time is 10 ns, and the TLB hit ratio is 90% (assuming 1-level page table):
A.
110 ns
B.
120 ns
C.
130 ns
D.
200 ns
Explanation & Key
Correct Answer:
6
Why do modern 64-bit operating systems use Multi-Level (Hierarchical) or Inverted Page Tables?
A.
Single-level page tables for a 64-bit space would be absurdly huge (exceeding terabytes of RAM per process just to store the table)
B.
Single-level tables cannot support C++ code
C.
Multi-level page tables speed up TLB misses
D.
Multi-level tables prevent page faults entirely
Explanation & Key
Correct Answer:
7
In variable-partition memory allocation, which dynamic placement algorithm typically has the best overall speed and memory utilization?
A.
Worst-Fit (allocates largest available hole)
B.
First-Fit (allocates the first hole that is big enough)
C.
Random-Fit
D.
Reverse-Fit
Explanation & Key
Correct Answer:
8
What is an Inverted Page Table?
A.
A page table stored in reverse alphabetical order
B.
A page table that has exactly one entry for each physical frame of real memory, indexed by frame number rather than virtual page number
C.
A page table that swaps rows and columns
D.
A page table stored in the CPU cache
Explanation & Key
Correct Answer:
9
How does Segmentation differ fundamentally from Paging?
A.
Paging divides memory into user-visible variable logical segments; segmentation divides into fixed physical blocks
B.
Paging divides memory into fixed-size physical blocks (transparent to programmer); Segmentation divides memory into variable-sized logical units (code, stack, data, heap) reflecting the programmer's view
C.
Segmentation uses a TLB; paging does not
D.
Paging requires hardware support; segmentation does not
Explanation & Key
Correct Answer:
10
What happens during address translation in a segmented memory system if the offset $d$ is greater than or equal to the Segment Limit?
A.
The segment expands automatically
B.
A hardware addressing trap (Segmentation Fault) is thrown, terminating the offending program
C.
The CPU loops back to offset 0
D.
The segment is swapped to disk
Explanation & Key
Correct Answer:
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